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general description the max1895/max1995 integrated controllers are opti- mized to drive cold-cathode fluorescent lamps (ccfl) using a synchronized full-bridge inverter architecture. synchronized drive provides near sinusoidal wave- forms over the entire input range to maximize the life of ccfls. the controllers also operate over a wide input voltage range with high efficiency and broad dimming range. the max1895/max1995 include safety features that limit the transformer secondary voltage and protect against single-point fault conditions including lamp-out and short-circuit faults. the max1895/max1995 regulate the ccfl brightness in three ways: linearly controlling the lamp current, digi- tal pulse-width modulating (dpwm) the lamp current, or using both methods simultaneously to achieve the widest dimming range (>30:1). ccfl brightness can be controlled with either an analog voltage (both max1895 and max1995) or a two-wire smbus com- patible interface (max1895 only). the max1895/max1995 directly drive the four external n-channel power mosfets of the full-bridge inverter. an internal 5.3v linear regulator powers the mosfet drivers, the synchronizable dpwm oscillator, and most of the internal circuitry. the max1895/max1995 are available in the space-saving 28-pin thin qfn package and operate over the -40? to +85? temperature range. applications notebook computers car navigation displays lcd monitors point-of-sale terminals portable display electronics features synchronized-to-resonant frequency good crest factor for longer lamp life ensures maximum strike capability high power to light efficiency wide dimming range (3 methods) lamp current adjust: >3 to 1 digital pwm (dpwm): >10 to 1 combined: >30 to 1 feed-forward for fast response to step change of input voltage wide input voltage range (4.6v to 28v) transformer secondary voltage limiting to reduce transformer stress lamp-out protection with 2s timeout short-circuit and other single-point fault protections synchronizable dpwm frequency dual-mode brightness control interface smbus serial interface (max1895 only) analog interface (both devices) high-accuracy analog interface separate 100% brightness voltage reference pin (crfsda) separate minimum lamp-current set-point pin (mindac) small footprint 28-pin thin qfn (5mm x 5mm) package max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ________________________________________________________________ maxim integrated products 1 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 max1895 thin qfn top view ref ilim mindac gnd mode crf/sda ctl/scl v cc batt ccv cci ifb n.c. v fb gh2 lx2 bst2 bst1 lx1 gh1 gl1 gl2 pgnd v dd n.c. n.c. n.c. sh/sus pin configurations 19-2157; rev 1; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package max1895 eti -40 c to +85 c 28 thin qfn 5 ? 5 max1895egi* -40 c to +85 c 28 qfn 5 ? 5 max1995 eti -40 c to +85 c 28 thin qfn 5 ? 5 max1995egi* -40 c to +85 c 28 qfn 5 ? 5 smbus is a trademark of intel corp. pin configurations continued at end of data sheet. * contact factory for availability.
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. batt to gnd..........................................................-0.3v to +30v bst1, bst2 to gnd ...............................................-0.3v to +36v bst1 to lx1, bst2 to lx2 ........................................-0.3v to +6v gh1 to lx1 ...............................................-0.3v to (bst1 + 0.3v) gh2 to lx2 ...............................................-0.3v to (bst2 + 0.3v) v cc , v dd to gnd .....................................................-0.3v to +6v ref, ilim to gnd .......................................-0.3v to (v cc + 0.3v) gl1, gl2 to gnd .......................................-0.3v to (v dd + 0.3v) mindac, ifb, ccv, cci to gnd .............................-0.3v to +6v mode to gnd ...........................................................-6v to +12v v fb to gnd..................................................................-6v to +6v crf/sda, ctl/scl, sh /sus to gnd ......................-0.3v to +6v pgnd to gnd .......................................................-0.3v to +0.3v continuous power dissipation (t a = +70 c) 28-pin qfn (derate 20.84mw/ c above +70 c) .......1667mw operating temperature range ...........................-40 c to +85 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c electrical characteristics (v batt = 12v, mindac = gnd, v cc = v dd , v sh /sus = 5.3v, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) (note1) parameter conditions min typ max units v cc = v dd = v batt 4.6 5.5 v batt input voltage range v cc = v dd = open 5.5 28 v v batt = 28v 3.2 6 v batt quiescent current v sh /sus = 5.5v v batt = v cc = 5v 6 ma v batt quiescent current, shutdown sh /sus = 0 6 20 a v cc output voltage, normal operation v sh /sus = 5.5v, 6v < v batt < 28v 0 < i load < 20ma 5.0 5.35 5.5 v v cc output voltage, shutdown sh /sus = gnd, no load 3.5 4.6 5.5 v v cc rising (leaving lockout) 4.5 v cc undervoltage lockout threshold v cc falling (entering lockout) 4 v v cc undervoltage lockout hysteresis 200 mv v cc por threshold rising edge 0.9 1.75 2.7 v v cc por hysteresis falling edge 50 mv ref output voltage, normal operation 4.5v < v cc < 5.5v, i load = 40a 1.96 2.00 2.04 v gh1, gh2, gl1, gl2 on-resistance i test = 100ma, v cc = v dd = 5.3v 2 6 ? gh1, gh2, gl1, gl2 maximum output current 1a bst1, bst2 leakage current bst_ = 12v, lx_ = 7v 5 a input resonant frequency guaranteed by design 20 300 khz minimum off-time 200 300 400 ns maximum off-time 20 30 40 s maximum current-limit threshold lx1-gnd, lx2-gnd (fixed) ilim = v cc 180 200 220 mv v ilim = 0.5v 80 100 120 maximum current-limit threshold lx1-gnd, lx2-gnd (adjustable) v ilim = 2.0v 370 400 430 mv
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v batt = 12v, mindac = gnd, v cc = v dd , v sh /sus = 5.3v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) (note1) parameter conditions min typ max units minimum current-crossing threshold lx1-gnd, lx2-gnd 6mv current-limit leading-edge blanking 200 300 400 ns d/a converter resolution guaranteed monotonic 5 bits mindac input voltage range 0 2 v mindac input bias current -2 +2 a mindac digital pwm disable threshold mindac = v cc 2.4 3.5 4.0 v ifb input voltage range 0 1.7 v v mindac = 0, dac code = 11111 binary 368 388 408 v mindac = 0, dac code = 00100 binary 30 50 70 ifb regulation point v mindac = 1v, dac code = 00000 binary 180 200 220 mv ifb input bias current -2 +2 a ifb lamp-out threshold 125 150 175 mv ifb to cci transconductance 1v < v cci < 2.5v 100 s cci output impedance 20 m ? v fb input voltage range -2 +2 v v fb input bias current v fb = 0 -0.5 0.5 a v fb regulation point 490 510 530 mv v fb to ccv transconductance 1v < v ccv < 2.7v 40 s v fb zero-voltage crossing threshold -10 +10 mv ccv output impedance 20 m ? no ac signal on mode 205 220 235 32khz ac signal on mode 250 digital pwm chop-mode frequency 100khz ac signal on mode 781 hz mode to dpwm sync ratio f mode /f dpwm 128 no ac signal on mode 2.10 2.33 2.60 32khz ac signal on mode 2.05 lamp-out detection timeout timer (note 2) v ifb < 0.1v 100khz ac signal on mode 0.66 s mode operating voltage range -5.5 +11.0 v mode input current mode = gnd or v cc -1 +1 a positive analog interface mode mode = gnd threshold (v ctl/scl = 0 sets minimum brightness) sync clock average value on mode to sync dpwm oscillator, not in shutdown. (note 3) 0.6 v negative analog interface mode mode = ref threshold (v ctl/scl = 0 sets maximum brightness = 0) sync clock average value on mode to sync dpwm oscillator, not in shutdown. (note 3) 1.4 2.6 v smbus interface mode mode = v cc threshold sync clock average value on mode to sync dpwm oscillator, not in shutdown. (note 3) v cc - 0.6 v
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v batt = 12v, mindac = gnd, v cc = v dd , v sh /sus = 5.3v, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) (note1) parameter conditions min typ max units mode ac signal amplitude peak-to-peak (note 4) 2 5 v mode ac signal synchronization range chopping oscillator synchronized to mode 32 100 khz crf/sda input range 2.7 5.5 v v crf/sda = 5.5v, sh /sus = v cc 20 crf/sda input current v crf/sda = 5.5v, sh /sus = 0 -1 +1 a ctl/scl input range 0 v crf / sda v ctl/scl input current mode = ref or gnd -1 +1 a a/d converter resolution guaranteed monotonic 5 bits a/d converter hysteresis 1 lsb sh /sus input low voltage 0.8 v sh /sus input high voltage 2.1 v sh /sus input hysteresis 300 mv sh /sus input bias current -1 +1 a sda, scl input low voltage 0.8 v sda, scl input high voltage 2.1 v sda, scl input hysteresis 300 mv sda output low sink current v crf/sda = 0.4v 4 ma scl serial clock high period t high 4s scl serial clock low period t low 4.7 s start condition setup-time t su:sta 4.7 s start condition hold-time t hd:sta 4s sda valid to scl rising-edge setup time, slave clocking in data t su:dat 250 ns scl falling-edge to sda transition t hd:dat 0ns scl falling-edge to sda valid, reading out data t dv 700 ns electrical characteristics (v batt = 12v, mindac = gnd, v cc = v dd , v sh /sus = 5.3v, t a = -40 c to +85 c , unless otherwise noted.) (note1) parameter conditions min typ max units v cc = v dd = v batt 4.6 5.5 v batt input voltage range v cc = v dd = open 5.5 28.0 v v batt = 28v 6 v batt quiescent current v sh /sus = 5.5v v batt = v cc = 5v 6 ma v batt quiescent current, shutdown v sh /sus = 0 20 a
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers _______________________________________________________________________________________ 5 electrical characteristics (continued) (v batt = 12v, mindac = gnd, v cc = v dd , v sh /sus = 5.3v, t a = -40 c to +85 c , unless otherwise noted.) (note1) parameter conditions min typ max units v cc output voltage, normal operation v sh /sus = 5.5v, 6v < v batt < 28v 0 < i load < 20ma 5.0 5.5 v v cc output voltage, shutdown sh /sus = gnd, no load 3.5 5.5 v v cc rising (leaving lockout) 4.5 v cc undervoltage lockout threshold v cc rising (entering lockout) 4.0 v v cc por threshold rising edge 0.9 2.7 v ref output voltage, normal operation 4.5v < v cc < 5.5v, i load = 40a 1.96 2.04 v gh1, gh2, gl1, gl2 on-resistance i test = 100ma 10 ? note 1: specifications to -40 c are guaranteed by design based on final test characterization results. note 2: corresponds to 512 dpwm cycles or 65536 mode cycles. note 3: the mode pin thresholds are only valid while the part is operating. when in shutdown v ref = 0 and the part only differenti- ates between smb mode and adc mode. when in shutdown and with adc mode selected the crf/sda and ctl/scl pins are at high impedance and will not cause extra supply current when their voltages are not at gnd or v cc . note 4: the amplitude is measured with the following circuit: v amplitude > 2v mode 500pf 10k ?
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 6 _______________________________________________________________________________________ 10 5 0 20 15 25 v cc vs. v batt max1895 toc09 v batt (v) v cc (v) 1 2 3 0 5 6 4 normal operation shutdown 1ms/div startup 0v 12v v batt v fb 2v/div ifb 2v/div max1895 toc04 i batt 500ma/div 1ms/div synchronized dpwm (f mode = 100khz, dpwm = 50%) v fb 1v/div ifb 1v/div lx1 10v/div lx2 10v/div max1895 toc05 1ms/div synchronized dpwm (f mode = 32khz, dpwm = 50%) v fb 1v/div ifb 1v/div lx1 10v/div lx2 10v/div max1895 toc06 2ms/div lamp-out voltage limiting v fb 2v/div v secondary 2kv/div ifb 1v/div max1895 toc07 lamp removed 400ms/div lamp-out protection v secondary 2kv/div v fb 2v/div ifb 1v/div max1895 toc08 2s lamp removed typical operating characteristics (v batt = 12v, v ctl = v crf, v mindac = 1v, mode = gnd, circuit of figure 1, table 4.) 10 s/div low input voltage operation (v batt = 8v) ifb 2v/div v fb 2v/div lx1 10v/div lx2 10v/div max1895 toc01 10 s/div high input voltage operation (v batt = 20v) ifb 2v/div v fb 2v/div lx1 10v/div lx2 10v/div max1895 toc02 20 s/div feed-forward compensation 10v v batt 20v v fb 2v/div ifb 2v/div max1895 toc03 lx1 10v/div
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers _______________________________________________________________________________________ 7 5.40 5.10 0.01 0.1 10 100 v cc load regulation 5.15 5.30 5.35 max1895 toc10 i load (ma) v cc (v) 1 5.20 5.25 normal operation shutdown 4.6 4.0 4.1 4.4 4.5 4.2 4.3 shutdown v cc (v) -15 -40 60 35 10 85 v cc vs. temperature max1895 toc11 temperature ( c) v cc (v) 5.32 5.33 5.31 5.35 5.36 5.34 shutdown v cc (v) 4.40 4.45 4.35 4.55 4.60 4.50 normal operation shutdown typical operating characteristics (continued) (v batt = 12v, v ctl = v crf, v mindac = 1v, mode = gnd, circuit of figure 1, table 4.) pin name function 1 ilim current-limit threshold adjustment. bias ilim with a resistive voltage-divider between ref or v cc and gnd. the current-limit threshold measured between lx_ and gnd is 1/5th of the voltage at ilim, ilim adjustment range is 0 to 3v. connect ilim to v cc to set the default current-limit threshold to 0.2v. 2 ref 2v reference output. bypass ref to gnd with a 0.1f capacitor. ref is discharged to gnd when shutdown. 3 mindac dac zero-scale input. v mindac sets the d/a converter s minimum-scale output voltage. disable dpwm by connecting mindac to v cc . 4 gnd system ground. the gnd input to the maximum and minimum current-limit comparators. the comparators sense the low-side fet nl1 and nl2 for zero-current crossing and current limit. 5 mode interface selection input and sync input for dpwm chopping. the average voltage on the mode pin selects one of three ccfl brightness control interfaces: mode = v cc enables smbus serial interface. mode = gnd enables the analog interface (positive analog interface mode), v ctl/scl = 0 sets minimum brightness. mode = ref enables the analog interface (reverse analog interface mode), v ctl/scl = 0 sets maximum brightness. an ac clocking signal superimposed on the dc average mode pin voltage can be used to synchronize the dpwm chopping frequency. see synchronizing the dpwm frequency . 6 crf/sda reference and serial data input. in analog interface mode, pin 6 is the reference input to the 5-bit brightness control adc. bypass crf to gnd with a 0.1f capacitor. in smbus interface mode (max1895 only), sda is an smbus serial data input/open-drain output. pin description
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 8 _______________________________________________________________________________________ pin name function 7 ctl/scl brightness control and serial clock input. in analog interface mode, pin 7 is a ccfl brightness control input. ctl varies from 0v to ref to linearly control lamp brightness. in smbus interface mode (max1895 only), scl is an smbus serial clock input. 8 sh /sus shutdown and suspend mode control. in analog interface mode, pin 8 is an active-low shutdown input. in smbus interface mode (max1895 only), pin 8 is an smbus suspend control input. 9, 10, 11, 23 n.c. no connection. not internally connected. 12 v dd power supply for gate drivers. connect v dd to the output of the linear regulator (v cc ). bypass v dd with a 0.1f capacitor to pgnd. 13 pgnd power ground. gate-driver current flows through this pin. 14 gl2 low-side fet nl2 gate-driver output 15 gl1 low-side fet nl1 gate-driver output 16 gh1 high-side fet nh1 gate-driver output 17 lx1 switching node connection. lx1 is the internal lower supply rail for the gh1 high-side gate driver. lx1 is also the sense input to the current comparators. 18 bst1 high-side fet nh1 driver bootstrap input. connect bst1 through a diode to v dd and through a 0.1f capacitor to lx1. (see figure 1.) 19 bst2 high-side fet nh2 driver bootstrap input. connect bst2 through a diode to v dd and through a 0.1f capacitor to lx2. (see figure 1.) 20 lx2 switching node connection. lx2 is the internal lower supply rail for the gh2 high-side gate driver. lx2 is also the sense input to the current comparators. 21 gh2 high-side fet nh2 gate-driver output 22 v fb lamp-output feedback-sense input. the average value on v fb is regulated during startup and open-lamp conditions to 0.5v by controlling the on time of high-side switches. a capacitive voltage- divider between the ccfl lamp output and gnd is sensed to set the maximum average lamp output voltage. 24 ifb lamp current-sense input. the voltage on ifb is used to regulate the lamp current. if the ifb input falls below 150mv for 2 seconds, then the max1895/max1995 signals an open-lamp fault. 25 cci current-loop compensation pin. cci is the output of the current-loop transconductance amplifier (gmi) that regulates the ccfl current. the cci voltage controls the time interval in which full- bridge applies the input voltage (batt) to transformer network. connect cci to gnd through a 0.1f capacitor. cci is internally discharged to gnd in shutdown. 26 ccv voltage-loop compensation pin. ccv is the output of the voltage-loop transconductance amplifier (gmv) that regulates the maximum average secondary transformer voltage. load ccv to gnd with a 10nf capacitor. the pin voltage controls the time interval that the full bridge applies the input voltage (batt) to transformer network. ccv is internally discharged to gnd in shutdown. 27 batt supply input. input to the internal 5.3v linear regulator that provides power (v cc ) to the chip. bypass batt to gnd with a 0.1f capacitor. 28 v cc 5.3v linear-regulator output. v cc is the supply voltage for the max1895. bypass v cc to gnd with a 0.47f ceramic capacitor. v cc can also be connected to batt if v batt < 5.5v. pin description (continued)
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers _______________________________________________________________________________________ 9 detailed description the max1895/max1995 are optimized to drive cold- cathode fluorescent lamps (ccfl) using a synchro- nized full-bridge inverter architecture. the drive to the full-bridge mosfets is synchronized to the resonant frequency of the tank circuit so that the ccfl s full- strike voltage develops for all operating conditions. the synchronized architecture provides near sinusoidal drive waveforms over the entire input range to maxi- mize the life of ccfls. the max1895/max1995 operate over a wide input voltage range (4.6v to 28v), achieve high efficiency, and maximize dimming range. the max1895/max1995 regulate the brightness of a ccfl in 3 ways: 1) linearly controlling the lamp current. 2) digitally pulse-width modulating (or chopping) the lamp current (dpwm). 3) using both methods simultaneously for widest dim- ming range. dpwm is implemented by pulse-width modulating the lamp current at a rate faster than the eye can detect. the max1895/max1995 include a 5.3v linear regulator to power the drivers for full-bridge switches, the syn- chronizable dpwm oscillator, and most of the internal circuitry. the max1895 is very flexible and can be con- trolled with an analog interface or with an smbus inter- face. the max1995 only supports analog interface. figure 1. standard application circuit max1895 ref ilim mindac gnd mode crf/sda ctl/scl gh2 lx2 bst2 bst1 lx1 c3 c2 t1 c1 c6 on/off reference input control input r3 c10 c8 c7 c5 d2-1 c9 d2-2 gh1 gl1 v cc batt ccv cci ifb v fb gl2 pgnd v dd sh/sus nl1 nl2 nh1 nh2 c4 r2 r4 r1 d1 vin 5v to 28v ccfl
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 10 ______________________________________________________________________________________ resonant operation the max1895/max1995 drive the four n-channel power mosfets that make up the zero-voltage switch- ing (zvs) full-bridge inverter as shown in figure 1. the lx1 and lx2 switching nodes are ac coupled to the primary side of the transformer. assume that nh1 and nl2 are turned on at the begin- ning of the cycle as shown in figure 2(a). the primary current flows through mosfet nh1, dc blocking cap c2, the primary side of transformer t1, and finally mos- fet nl2. during this interval, the primary current ramps up until the controller turns off nh1. when nh1 is off, the primary current forward biases the body diode of nl1 and brings the lx1 node down as shown in figure 2(b). when the controller turns on nl1, its drain-to- source voltage is near zero because its forward-biased body diode clamps the drain. since nl2 is still on, the primary current flows through nl1, c2, the primary side of t1, and finally nl2. once the primary current drops to the minimum current threshold (6mv/r dson ), the controller turns off nl2. the remaining energy in t1 charges up the lx2 node until the body diode of nh2 is forward biased. when nh2 turns on, it does so with near zero drain-to-source voltage. the primary current reverses polarity as shown in figure 2(c), beginning a new cycle with the current flowing in the opposite direc- tion, with nh2 and nl1 on. the primary current ramps up until the controller turns off nh2. when nh2 is off, the primary current forward biases the body diode of nl2, and brings the lx2 node down as shown in figure 2(d). after the lx2 node goes low, the controller loss- lessly turns on nl2. once the primary current drops to the minimum current threshold, the controller turns off nl1. the remaining energy charges up the lx1 node until the body diode of nh1 is forward biased. finally, nh1 losslessly turns on, beginning a new cycle as shown in figure 2(a). figure 2. resonant operation v batt nh1 on nh2 off nl1 off nl2 on t1 (a) c2 v batt nh1 off nh2 off nl1 on (body diode turns on first) nl2 on t1 (b) c2 v batt nh1 off nh2 on nl1 on (body diode turns on first) nl2 off t1 (c) c2 v batt nh1 off nh2 off nl1 on nl2 on t1 (d) c2 lx1 lx2 lx1 lx2 lx1 lx2 lx1 lx2
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 11 note that switching transitions on all four power mosfets occur under zvs conditions, which reduces transient power losses and emi. the equivalent circuit of the resonant tank is shown in figure 3. the resonant frequency is determined by the rlc resonant tank elements: c s , c p , l l , and rb. cs is the series capacitance on the primary side of the trans- former. c p is the parallel cap on the transformer s sec- ondary. l l is the transformer secondary leakage inductance. rb is an idealized resistance which models the ccfl load in normal operation. current and voltage control loops the max1895/max1995 use a current loop and a volt- age loop to control the energy applied to the ccfl. the current loop is the dominant control in setting the lamp brightness. the rectified lamp current is measured with a sense resistor in series with the ccfl. the voltage across this resistor is applied to the ifb input to regulate the average lamp current. the voltage loop controls the voltage across the lamp and is active during the begin- ning of dpwm on-cycles and the open-lamp fault condi- tion. it limits the energy applied to the resonant network once the transformer secondary voltage is above the threshold of 500mv average measured at v fb . both voltage and current circuits use transconduc- tance-error amplifiers to compensate the loops. the voltage-error amplifier creates an error current based upon the voltage difference between v fb and the inter- nal reference level (typically 500mv) (figure 4). the error current is then used to charge and discharge a capacitor at the ccv output (c ccv ) to create an error voltage c ccv . the current loop produces a similar sig- nal at cci based on the voltage difference between ifb and the dimming control signal. this signal is set by either the smbus interface (max1895 only) or the ana- log interface (both max1895 and max1995) (see dimming range section). this error voltage is called v cci . in normal operation, the current loop is in control of the regulator so long as v cci is less than v ccv . the control signal is compared with an internal ramp signal to set the high-side switch on time (t on ). when dpwm is employed, the two control loops work together to limit the transformer voltage and to allow wide dimming range with good line rejection. during the dpwm off-cycle, v ccv is set to 1.2v and the current- loop error amplifier output is high impedance. v vfb is set to 0.6v to create a soft-start at the beginning of each dpwm on-cycle in order to avoid overshoot on the trans- former s secondary. when the transconductance amplifi- er in the current loop is high impedance, it acts like a sample-and-hold circuit, to keep v cci from changing during the off-cycles. this action allows the current con- trol loop to regulate the average lamp current. see the current sense resistor and the voltage sense capacitors sections for information regarding setting the current- and voltage-loop thresholds. startup operation during startup differs from the steady-state condition described in the current and voltage loop section. upon power-up, v cci slowly rises, increasing the duty cycle, which provides soft-start. during this time, v ccv , which is the faster control loop, is limited to 150mv above v cci . once the secondary voltage reach- es the strike voltage, the lamp current begins to increase. when the lamp current reaches the regulation point, v cci exceeds v ccv and it reaches steady state. with mindac = v cc , dpwm is disabled and the cur- rent loop remains in control regulating the lamp current. feed-forward control the max1895/max1995 have a feed-forward control circuit, which influences both control loops. feed-for- ward control instantly adjusts the t on time to changes in input voltage. this feature provides immunity to changes in input voltage at all brightness levels and makes compensation over wide input ranges easier. the feed-forward circuit improves line regulation for short dpwm on times and makes startup transients less dependent on input voltage. feed-forward control is implemented by varying the internal voltage ramp rate. this has the effect of varying t on as a function of input voltage while maintaining about the same signal levels at v cci and v ccv . since the required voltage change across the compensation capacitors is minimal, the controller s response to change in v batt is essentially instantaneous. figure 3. equivalent circuit li rb ac source ac source ccfl 1:n c s c p c p c s /(nxn)
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 12 ______________________________________________________________________________________ transient overvoltage protection from dropout the max1895/max1995 are designed to maintain tight control of the transformer secondary under all transient conditions including dropout. to maximize run time, it is desirable to allow the circuit to operate in dropout at extremely low battery voltages where the backlight s performance is not critical. when v batt is very low, the controller can lose regulation and run at maximum duty cycle. under these circumstances, a transient overvolt- age condition could occur when the ac adapter is sud- denly applied to power the circuit. but the feed-forward circuitry minimizes variations in lamp voltage due to such input voltage steps. the regulator also clamps the voltage on v cci . both features ensure that overvoltage transients do not appear on the transformer when leav- ing dropout. the v cci clamp is unique in that it limits at the peaks of the voltage-ramp generator. as the circuit reaches dropout, v cci approaches the peaks of the ramp gen- erator in order to reach maximum t on . if v batt decreases further, the control loop loses regulation and v cci tries to reach its positive supply rail. the clamp on v cci prevents this from happening and v cci rides just above the peaks of the pwm ramp. if v batt continues to decrease, the feed-forward pwm ramp generator loses amplitude and the clamp drags v cci down with it to a voltage below where v cci would have been if the circuit were not in dropout. when v batt suddenly steps out of dropout, v cci is still low and maintains the drive on the transformer at the old dropout level. the control bst1 bst2 gh1 lx1 gh2 lx2 gl1 gl2 pgnd ccfl sh/sus mindac crf/sda ctl/scl mode ccv v fb cci ifb lx2 lx1 ilmit gnd ref batt v cc ref supply 0.15v 0.5v gmv gmi 4mv gnd v dd dpwm osc lamp current and dpwm control smbus dpwm comp pwm comp mindac = v cc y = 1, n =0 ramp generator imin comp imax comp control logic peak detector pk_det clamp ccv clamp mux max1895 max1995 reference input control input figure 4. functional diagram
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 13 loop then slowly corrects and increases v cci to bring the circuit back into regulation. interface selection table 1 describes the functionality of sh /sus, crf/ sda, and ctl/scl in each of the max1895 s three interface modes. the max1895 features both an smbus digital interface and an analog interface. note that the mode signal can also synchronize the dpwm frequency. (see synchronizing the dpwm frequency. ) dimming range the brightness is controlled by either the analog interface (for both max1895 and max1995, see analog interface section) or the smbus interface (for max1895 only, see smbus interface section). the brightness of the ccfl is adjusted in the following three ways: 1) lamp-current control, where the magnitude of the average lamp current is adjusted. 2) dpwm control, where the average lamp current is pulsed to the set level with a variable duty cycle. 3) the combination of the first two methods. in each of the three methods, a 5-bit brightness code is generated from the selected interface and is used to set the lamp current and/or dpwm duty cycle. the 5-bit brightness code defines the lamp current level with 00000\b representing minimum lamp current and 11111\b representing maximum lamp current. the average lamp current is measured across an external sense resistor (see current-sense resistor section). the voltage on the sense resistor is measured at ifb. the brightness code adjusts the regulation voltage at ifb (v ifb ). the minimum average v ifb is v mindac /5 (v mindac = 0~2v) and the maximum average is set by the following formula: v ifb = v ref ? 31/160 +v mindac /160 which is between 387.5mv and 400mv. if v ifb does not exceed 150mv peak (which is about 47.7mv/r1 rms lamp current) for greater than 2s, the max1895/max1995 assumes a lamp-out condition and shuts down (see lamp-out detection section). the equation relating brightness code to ifb regulation voltage is: v ifb = v ref ? n/160 + v mindac ? (32 - n)/160 where n is the brightness code. to always use maximum average lamp current when using dpwm control, set v mindac to v ref . dpwm control works similarly to lamp-current control as it also responds to the 5-bit brightness code. a bright- ness code of 00000\b corresponds to a 9% dpwm duty cycle and a brightness code of 11111\b corresponds to a 100% dpwm duty cycle. the duty cycle changes by 3.125% per step, but codes 00000\b to 00011\b all pro- duce 9% (figure 5). to disable dpwm and always use 100% duty cycle, set v mindac to v cc . note that with dpwm disabled, the equations shown above should assume v mindac = 0 instead of v mindac = v cc . table 2 describes min- dac s functionality and table 3 shows some typical settings for the brightness adjustment. in normal operation, v mindac is set between 0 and v ref and the max1895/max1995 use both lamp-cur- rent control and dpwm control to vary the lamp bright- ness. in this mode, lamp-current control regulates the average lamp current during a dpwm on-cycle. analog interface and brightness code the max1895/max1995 s analog interface uses an internal adc with 1-bit hysteresis to generate the bright- ness code used to dim the lamp (see dimming range section). ctl/scl is the adc s input and crf/sda is its reference voltage. the adc can operate in either posi- tive-scale adc mode or negative-scale adc mode. in positive-scale adc mode, the brightness code increas- es from 0 to 31 as v ctl increases from 0 to v crf . in table 1. interface modes digital interface (max1895 only) analog interface pin mode = vcc mode = ref v ctl/scl = 0 = maximum brightness mode = gnd v ctl/scl = 0 = minimum brightness sh /sus smbus suspend logic level shutdown control input crf/sda smbus data i/o reference input for minimum brightness reference input for maximum ctl/scl smbus clock input analog control input to set brightness (range from 0 to crf/sda)
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 14 ______________________________________________________________________________________ negative-scale mode, the brightness scale decreases from 31 to 0 as v ctl increases from 0 to v crf . the analog interface s internal adc uses 1-bit hystere- sis to keep the lamp from flickering between two codes. v ctl s positive threshold (v ctl(th) ) is the voltage required to transition the brightness code as v ctl increases and can be calculated as follows: figure 6. combined power level 0 10 20 30 60 70 40 50 80 90 100 012 48 20 16 24 28 32 brightness code combined power level (%) combined power level (both dpwm and lamp-control current) figure 5. dpwm settings 0 10 20 30 60 70 40 50 80 90 100 012 48 20 16 24 28 32 brightness code dpwm duty cycle (%) dpwm settings table 2. mindac functionality condition function mindac = v cc dpwm disabled (always on 100% duty cycle). operates in lamp-current control only. (use v mindac = 0 in the equations.) mindac = ref dpwm control enabled, duty cycle ranges from 9% to 100%. lamp-current control is disabled (always maximum current). 0 v mindac < v ref the device uses both lamp-current control and dpwm. table 3. brightness adjustment ranges range positive-scale adc mode negative-scale adc mode smbus dac output dpwm duty cycle combined power level maximum brightness mode = gnd v crf/sda = v ctl/scl mode = ref v crf/sda = 0 bright [4:0] = 11111 full-scale dac output = 387.5mv 100% 100% minimum brightness mode = gnd v crf/sda = 0 v mindac = 1/3v ref mode = ref v crf/sda = v ctl/scl v mindac = 1/3v ref bright [4:0] = 00000 v mindac = 1/3v ref zero-scale dac output = v mindac / 5 9% 3% note: the current level range is solely determined by the mindac to ref ratio and is externally set.
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 15 v ctl(th) = (n + 2)/33 v crf (positive-scale adc mode, mode = gnd) v ctl(th) = (33 - n)/33 v crf (negative-scale adc mode, mode = ref) v ctl s negative threshold is the voltage required to transition the brightness code as v ctl decreases and can be calculated as follows: v ctl(th) = n/33 v crf (positive-scale adc mode, mode = gnd) v ctl(th) = (31 - n)/33 v crf (negative-scale adc mode, mode = ref) where n is the brightness code. see figure 7 for a graphical representation of the thresholds. see the digital interface section for instructions on using the smbus interface. unlike conventional dimming control circuits that have separate supplies and require additional minimum brightness circuitry, the max1895/max1995 provide dedicated pins for dimming control. the advantages of the max1895/max1995 s analog interface are illustrat- ed in figure 8. the analog interface is very simple in that the output voltage range of the dimming control cir- cuit matches the input voltage range of the inverter control ic. with this method it is possible to guarantee the maximum dimming range (figure 9). for the con- ventional interface, the control voltage and the input voltage have different ranges. to avoid nonuniform lighting across the ccfl tube, or the thermometer effect , the lower limits of maximum and minimum con- trol voltages have to be above the upper limits of the maximum and minimum input voltages, respectively. therefore, the useful dimming range is reduced. for the max1895/max1995 s analog interface, the control volt- age has the same range as the input voltage, so the useful dimming range is maximized. synchronizing the dpwm frequency mode has two functions: one is to select the interface mode as described in interface selection and the other is to synchronize the dpwm chopping frequency to an external signal to prevent unwanted artifacts in the display screen. to synchronize the dpwm frequency, connect mode to v cc , ref, or gnd through a 10k ? resistor. then connect a 500pf capacitor from an ac signal source to mode as shown in figure 10. the amplitude of the ac signal must be at least 2v peak-to-peak but no greater than 5v peak-to-peak for accurate operation. the tran- sition time of the ac signal should be less than 200s. the synchronization range is 32khz to 100khz, which figure 7. brightness code brightness code 31 30 29 3 2 1 0 1 33 2 33 3 33 4 33 v ctl v crf (mode = gnd) v ctl v crf (mode = ref) 30 33 31 33 32 33 1 32 33 31 33 30 33 29 33 3 33 2 33 1 33 0 1 figure 8. analog interface for dimming 0 to v max dimming control circuit vcca inverter controller vccb min. dim ckt. max1895 v ctl v ctl mindac v crf ref conventional interface max1895/max1995 interface dimming control circuit vcca vccb
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 16 ______________________________________________________________________________________ corresponds to a dpwm frequency range of 250hz to 781hz (128 mode pulses per dpwm cycle). high dpwm frequencies limit the dimming range. see loop compensation for more information concerning high dpwm frequencies. a simple oscillator circuit as shown in figure 11 can be used to generate the synchronization signal. the core of the oscillator is the max9031, which is a low-cost, single-supply comparator in a 5-pin sc70 package. the v cc and ref of the max1895/max1995 provide the supply voltage and the reference voltage for the oscillator. the positive threshold of the oscillator is: v th+ = (v cc + v ref )/2. the negative threshold is given by: v th+ = v ref /2. the frequency of the oscillator is calculated as follows: for c = 330pf, a 13k ? resistor generates a 100khz signal and a 39k ? resistor generates a 32khz signal. f rc vv v vv v th cc th th cc th = + ? ? ? ? + 1 ln () () figure 9. useful dimming range gnd gnd max. brightness control voltage tolerance min. brightness control voltage max. brightness input voltage min. brightness input voltage max. brightness control voltage tolerance min. brightness control voltage max. brightness input voltage min. brightness input voltage typical dimming range typical dimming range typical dimming range lost conventional interface max1895/max1995 interface
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 17 por and uvlo the max1895/max1995 include power-on reset (por) and undervoltage lockout (uvlo) circuits. the por resets all internal registers such as dac output, fault conditions, and all smbus registers. por occurs when v cc is below 1.5v. the smbus input-logic thresholds are only guaranteed to meet electrical characteristic limits for v cc as low as 3.5v, but the interface will con- tinue to function down to the por threshold. the uvlo is activated and disables both high-side and low-side switch drivers when v cc is below 4.2v (typ). low-power shutdown when the max1895/max1995 are placed in shutdown, all functions of the ic are turned off except for the 5.3v linear regulator that powers all internal registers and the smbus interface (max1895 only). the smbus interface is accessible in shutdown. in shutdown, the linear regu- lator output voltage drops to about 4.5v and the supply current is 6a (typ), which is the required power to maintain all internal register states. while in shutdown, lamp-out detection and short-circuit detection latches are reset. the device can be placed into shutdown by either writing to the shutdown mode register (max1895 smbus mode only) or with sh /sus. lamp-out detection for safety, the max1895/max1995 monitor the lamp current to detect the open-lamp fault. when the peak voltage on ifb drops below 150mv (ifb regulation point must be set above 48mv) the lamp-out timer starts. before the timer times out, v cci increases the sec- ondary voltage in an attempt to maintain lamp-current regulation. as v cci rises, v ccv rises with it until the sec- ondary voltage reaches its preset limit. at this point, v ccv stops and limits the secondary voltage by limiting t on . because v ccv is limited to 150mv above v cci the voltage control loop is able to quickly limit the sec- ondary voltage. without this clamping feature, the trans- former voltage would overshoot to dangerous levels because v ccv would take more time to slew down from its supply rail. if the peak voltage on ifb does not rise above 150mv before timeout, the max1895/max1995 shut down the full bridge. overcurrent fault detection and protection the max1895/max1995 sense overcurrent faults on each switching cycle. the current comparator monitors the voltage drop from lx_ to gnd. if the voltage exceeds the current-limit threshold, the regulator turns off the high-side switch to prevent the transformer pri- mary current from increasing further. applications information the max1895 s standard application circuit, shown in figure 1, regulates the current of a 4.5w ccfl. the ic s analog voltage interface sets the lamp brightness with a greater than 30 to 1 power adjustment range. this circuit operates from a wide supply voltage range of 4.6v to 28v. typical applications for this circuit include notebook, desktop monitor, and car navigation displays. table 4 shows the recommended compo- nents for the power stage of the 4.5w application. to select the correct component values, several c cfl parameters (table 6) and the dc input characteristics must be specified. mosfets the max1895/max1995 require four external switches nl1, nl2, nh1, and nh2 to form a full bridge to drive ccfl. the regulator senses drain-to-source voltage of nl1 and nl2 to detect the transformer primary mini- mum current crossing and overcurrent fault condition. figure 10. dpwm synchronization mode gnd dpwm synchronization signal 10k ? 500pf adc- adc+ smbus vl ref max1895 max1995 figure 11. a simple rc oscillator to mode 100k ? 1% 100k ? 1% r c ref v cc max9031
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 18 ______________________________________________________________________________________ r dson of nl1 and nl2 should be matched. select a dual logic-level n-channel mosfet with low r dson to minimize conduction loss for nl1/nl2 and nh1/nh2 (fairchild fdc6561). the regulator softly turns on each of four switches in the full bridge. zvs (zero-voltage switching) occurs when the external power mosfets are turned on while their respective drain-to-source voltages are near zero volts. zvs effectively eliminates the mosfet transition losses caused by c rss (drain- to-source capacitance) and parasitic capacitance dis- charge. zvs improves efficiency and reduces switching-related emi. table 4. components for the standard application circuit designation description recommended device manufacturer c1 4.7f, 25v, x5r ceramic capacitor tmk325bj475mn c3225x7r1e475m taiyo yuden www.t-yuden.com tdk www.tdk.com c2 1f, 25v, x7r ceramic capacitor tmk316bj105kl c3216x7r1e105k taiyo yuden tdk c3 15pf, 3.1kv, high-voltage ceramic capacitor ghm1038-sl-150j-3k c4520c0g3f150k murata www.murata.com tdk c4 0.015f, 16v, x7r ceramic capacitor emk105bj153kv grm36x7r153k016 taiyo yuden murata c5, c6, c7, c8, c10 0.1f,10v, x5r ceramic capacitors lmk105bj104mv grm36x5r104k010 c10055r1a104k taiyo yuden murata tdk c9 0.01f, 16v, x7r ceramic capacitor ecj-0eb1c103k panasonic www.panasonic.com d1 100ma dual-series diode mmbd4148se mmbd7000 cmpd7000 fairchild semiconductor www.fairchildsemi.com general semiconductor www.gensemi.com central semiconductor www.centralsemi.com bat54aw diodes incorporates www.diodes.com d2 100ma dual schottky diode common anode cmssh-3a central semiconductor fdc6561an fairchild semiconductor nh1/nl1, nh2/nl2 dual n-channel mosfets (30v, 0.095 ? , sot23-6) tpc6201 toshiba www.toshiba.com r1 150 ? 1% resistor r2 2k ? 5% resistor r3 100k ? 1% resistor r4 49.9k ? 1% resistor t1 1:100 transformer t912mg-1018 toko www.tokoam.com
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 19 current-sense resistor the max1895/max1995 regulate the ccfl average current through the sense resistor r1 in figure 1. the voltage at ifb is the half-wave rectified representation of the current through the lamp. the inverter regulates the average voltage at ifb, which is controlled by either the analog interface or the smbus interface. to set the maximum lamp rms current, determine r1 as follows: r1 = 0.444v/iccfl, rms, max, where iccfl, rms, max is the maximum rms lamp current. mindac and the wave shape influence the actual maximum rms lamp current. if necessary, use an rms current meter to make final adjustments to r1. voltage-sense capacitors the max1895/max1995 limit the transformer secondary voltage during open-lamp fault through the capacitive divider c3/c4. the voltage of v fb is proportional to ccfl voltage. to set the maximum rms secondary transformer voltage, choose c3 around 10pf to 22pf, and select c4 such that c4 = v t(max) /1.11v x c3, where v t(max) is the maximum rms secondary transformer voltage (above the strike voltage). r2 sets the v fb dc bias point to 0v. choose r2 =10/(c4 ? 6.28 ? f sw ), where f sw is the nominal resonant operating frequency. loop compensation cci sets the speed of the current loop that is used dur- ing startup, maintaining lamp current regulation, and during transients caused by changing the lamp-current settling. the typical cci capacitor value is 0.1f. larger values limit lamp-current overshoot, but increase setting time. smaller values speed up its response time, but extremely small values can lead to instability. ccv sets the speed of the voltage loop that affects startup, dpwm transients and operation in an open- tube fault condition. if dpwm is not used, the voltage control loop should only be active during startup or an open-lamp fault. the ccv capacitor typical value is 0.01f. use the smallest value of ccv capacitor nec- essary to set an acceptable fault-transient response and not cause excessive ringing at the beginning of a dpwm pulse. larger ccv capacitor values reduce transient overshoot, but can degrade regulation at low dpwm duty cycles by increasing the delay to strike voltage. resonant components the max1895/max1995 work well with air-gap trans- formers with turns ratio n in the order of n p :n s = 1:90 to 1:100 for most applications. the transformer sec- ondary resonant frequency must be controlled. a low- profile ccfl transformer typically operates between 50khz (f min ) and 200khz (f max ). the transformer t1, the dc blocking capacitor c2, the parallel capacitor c3, and the ccfl lamp form a resonant tank. the reso- nant frequency is determined by the transformer sec- ondary leakage inductance l, c2, and c3. the tank is a bandpass filter whose lower frequency is bounded by l, n, and c2. n is the transformer s turns ratio. choose c2 n 2 (10 ? f 2 min ? l). the upper frequency is bounded by l and c3. choose c3 1/(40 ? f 2 min ? l). other components the high-side mosfet drivers (gh1 and gh2) are powered by the external bootstrap circuit formed by d2, c5 and c6. connect bst1/bst2 through a dual signal-level schottky diode d2 to v dd , and connect it to lx1/lx2 with 0.1f ceramic capacitors. use a dual- series signal-level diode (d1) to generate the half-wave rectified current-sense voltage across r1. the current through these diodes is the lamp current. dual-lamp regulator the max1895/max1995 can be used to drive two ccfl tubes as shown in figure 12. see table 5 for component selection. the circuit consists of two identi- cal transformers with primary windings connected in parallel and secondary windings in series. the two transformers can also be replaced with a single trans- former, which has one primary winding and two sec- ondary windings. the advantage of the series secondary windings is that the same current flows through both lamps resulting in approximately the same brightness. in normal operation, c12 is charged to approximately 6v biasing n1 on, which permits current to flow in the loop as follows: in the first half-cycle, current flows through the secondary winding of t1, ccfl1, diode d1, mosfet n1, sense resistor r1, zener diode d4 (forward bias), ccfl2, finally returning to t2. in the second half-cycle the lamp current flows through t2, ccfl2, d4 (breakdown), d3 (forward bias), ccfl1, and back to t1. the roundabout path of current flow is necessary in order to detect an open-lamp condition when either ccfl is removed. if ccfl1 is open, the lamp current cannot flow through the sense resistor r1. when ifb drops below 150mv the controller detects the condition and shuts down after a 2s delay. during the delay cur- rent can flow from t2 through ccfl2, d4 (breakdown), and r6 back to t2. if ccfl2 is removed, the voltage across d4 drops to zero and c11 is discharged through r5. n1 is biased off which forces the voltage at ifb to drop to zero once again. during the 2s turn-off delay, current flows from t1 to ccfl1 through d3
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 20 ______________________________________________________________________________________ (breakdown) and r6 back to t1. d3 clamps the drain of n1 enabling the use of a mosfet with modest break- down characteristics. the secondary voltages of both transformers are moni- tored through the two identical capacitive voltage dividers (c3/c4 and c13/c11). the dual diode d6 rec- tifies the two sensed voltages and passes the signal to the vfb pin. a full-wave rectified sinusoidal waveform appears at the vfb pin. the rms value of this new vfb signal is greater than the half-wave rectified signal in the single-lamp application. to compensate for the waveform change and the forward voltage drop in the diodes, the capacitive voltage-divider ratio must be decreased. choose c3 around 10pf to 22pf, and select c4 according to c4 = v t, max /1.33v ? c3, where v t, max is the maximum transformer secondary rms voltage. layout guidelines careful pc board layout is critical to achieve low switching losses and clean, stable operation. the high voltage and switching power stages require particular attention (figure 13). the high-voltage sections of the layout need to be well separated from the control cir- cuit. most layouts are constrained to long narrow pc boards, so this separation occurs naturally. follow these guidelines for good pc board layout: 1) keep the high-current paths short and wide, espe- cially at the ground terminals. this is essential for stable, jitter-free operation, and high efficiency. figure 12. dual-lamp application circuit max1895 ref ilim mindac gnd mode crf/sda ctl/scl gh2 lx2 bst2 bst1 lx1 c3 c2 t1 t2 c1 c6 on/off reference input control input r3 c10 c8 c7 c5 d2-1 c9 d2-2 gh1 gl1 v cc batt ccv cci ifb v fb gl2 pgnd v dd sh/sus nl1 nl2 nh1 nh2 c4 r4 c12 c11 c13 d4 d5 d3 d6 r6 n1 r2 r7 r6 r5 r1 d1 vin 5v to 28v ccfl ccfl2
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 21 table 5. components for the dual-lamp application circuit designation description recommended device manufacturer c1 4.7f, 25v, x5r ceramic capacitor tmk325bj475mn c3225x7r1e475m taiyo yuden www.t-yuden.com tdk www.tdk.com c2 1f, 25v, x7r ceramic capacitor tmk316bj105kl c3216x7r1e105k taiyo yuden tdk c3, c13 15pf, 3.1kv, high-voltage ceramic capacitors ghm1038-sl-150j-3k c4520c0g3f150k murata www.murata. tdk c4, c11 0.015f, 16v, x7r ceramic capacitors emk105bj153kv grm36x7r153k016 taiyo yuden murata c5, c6, c7, c8, c10, c12 0.1f, 10v, x5r ceramic capacitors lmk105bj104mv grm36x5r104k010 c1005x5r1a104k taiyo yuden murata tdk c9 0.01f, 16v, x7r ceramic capacitor ecj-0eb1c103k panasonic www.panasonic.com d1, d5 100ma diodes mmbd4148 imbd4148 mmbd4148 fairchild semiconductor www.fairchildsemi.com general semiconductor www.gensemi.com diodes incorporated www.diodes.com d2 100ma dual schottky diode, common anode bat54aw cmssh-3a diodes incorporated central semiconductor www.centralsemi.com d3, d4 6.2v zener diodes cmpz5234b bzx84c6v2 central semiconductor diodes incorporated d6 dual diode, common cathode cmpd2838 bav70 central semiconductor diodes incorporated n1 n-channel mosfet (sot23) 2n7002 2n7002 2n7002 fairchild semiconductor general semiconductor central semiconductor nh1/nl1, nh2/nl2 dual n-channel mosfets (30v, 0.095 ? , sot23-6) fdc6561an tpc6201 fairchild semiconductor toshiba www.toshiba.com r1 150 ? 1% resistor r2, r6 2k ? 5% resistors r3 100k ? 1% resistor r4 49.9k ? 1% resistor r5 1k ? 5% resistor r7 20k ? 5% resistor t1, t2 1:100 transformers t912mg-1018 toko www.tokoam.com
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 22 ______________________________________________________________________________________ 2) utilize a star ground configuration for power and analog grounds. the power ground and analog ground should be completely isolated meeting only at the center of the star. the center should be placed at the backside contact to the qfn pack- age. using separate copper planes for these planes may simplify this task. quiet analog ground is used for ref, ccv, cci, rx, and mindac (if a resistive voltage-divider is used). 3) route high-speed switching nodes away from sensi- tive analog areas (ifb, vfb, ref, ilim). make all pin- strap control input connections (ilim, etc.) to analog ground or v cc rather than power ground or v dd . 4) mount the decoupling capacitor from v cc to gnd as close as possible to the ic with dedicated traces that are not shared with other signal paths. 5) the current sense paths for lx1 and lx2 to gnd must be made using kelvin sense connections to guarantee the current-limit accuracy. with so-8 mosfets, this is best done by routing power to the mosfets from outside using the top copper layer, while connecting gnd and lx inside (underneath) the so-8 package. 6) ensure the feedback connections are short and direct. to the extent possible, ifb and v fb connec- tions should be far away from the high voltage traces and the transformer. 7) to the extent possible, high-voltage trace clearance on the transformer s secondary should be widely separated. the high voltage traces should also be separated from adjacent ground planes to prevent capacitive coupling losses. figure 13. layout example note: dual mosfet n2 is mounted on the bottom side of the pc board directly under n1. high-current primary connection high-voltage secondary connection lamp n1 n2 t1 c4 c2 d1 r2 c3 table 6. ccfl specifications specification symbol units description ccfl minimum strike voltage ( kick-off voltage ) v s v rms although ccfls typically operate at <550v rms , a higher voltage (up to 1000v rms and beyond) is required initially to start the tube. the strike voltage is typically higher at cold temperatures and at the end of life of the tube. ccfl typical operating voltage ( lamp voltage ) v l v rms once a ccfl has been struck, the voltage is required to maintain light output falls to approximately 550v rms . shorter tubes may operate on as little as 250v rms . the operating voltage of the ccfl stays relatively constant, even as the tube s brightness is varied. ccfl maximum operating current ( lamp current ) i l ma rms the maximum ac current through a ccfl is typically 5ma rms . dc current is not allowed through ccfls. the maximum lamp current is set by the sense resistor, r1, and the maximum brightness setting. r1 = 2.2 ? v ifbmax /i lmax . ccfl maximum frequency ( lamp frequency ) f l khz the maximum ac lamp-current frequency. the max1895/max1995 are designed to operate between 20khz and 300khz.
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 23 8) the traces to the capacitive voltage-divider on the transformer s secondary need to be widely separat- ed to prevent arcing. moving these traces to oppo- site sides of the board can be beneficial in some cases (figure 13). digital interface with mode connected to v cc , the crf/sda and ctl/scl pins no longer behave as analog inputs; instead they function as an intel smbus-compatible two-wire digital interface. crf/sda is the bidirectional data line and ctl/scl is the clock line of the two-wire interface corresponding respectively to smbdata and smbclk lines of the smbus. the max1895 uses the write-byte, read-byte, send-byte, and receive-byte protocols (figure 14). the smbus protocols are docu- mented in system management bus specification v1.08 and are available at www.sbs-forum.org . the max1895 is a slave-only device and responds to the 7-bit address 0b0101101 (i.e., with the r w bit clear indicating a write, this corresponds to 0x5a). the max1895 has three functional registers: a 5-bit bright- ness register (bright4 bright0), a 3-bit shutdown mode register (shmd2 shmde0), and a 2-bit status register (status1 status0). in addition, the device has three identification (id) registers: an 8-bit chip id register, an 8-bit chip revision register, and an 8-bit manufacturer id register. crf/sda and ctl/scl pins have schmidt-trigger inputs that can accommodate slow edges; however, the rising and falling edges should still be faster than 1s and 300ns, respectively. communication starts with the master signaling the beginning of a transmission with a start condition, which is a high-to-low transition on crf/sda, while ctl/scl is high. when the master has finished com- municating with the slave, the master issues a stop condition (p), which is low-to-high transition on crf/sda, while ctl/scl is high. the bus is then free for another transmission. figures 15 and 16 show the timing diagram for signals on the 2-wire interface. the address-byte, command-byte, and data-byte are trans- mitted between the start and stop conditions. the crf/sda state is allowed to change only while 1b ack 1b 7 bits address ack 1b wr 8 bits data 1b ack p 8 bits s command write-byte format receive-byte format slave address command byte: selects which register you are writing to data byte: data goes into the register set by the command byte 1b ack 1b 7 bits address ack 1b wr s 1b ack 8 bits data 7 bits address 1b rd 1b 8 bits /// p s command slave address slave address command byte: sends command with no data; usually used for one- shot command command byte: selects which register you are reading from slave address: repeated due to change in data- flow direction data byte: reads from the register set by the command byte 1b ack 7 bits address 1b rd 8 bits data 1b /// p s data byte: reads data from the register commanded by the last read-byte or write-byte transmission; also used for smbus alert response return address s = start condition shaded = slave transmission wr = write = 0 p = stop condition ack= acknowledged = 0 rd = read =1 /// = not acknowledged = 1 1b ack 7 bits address 1b wr 8 bits command 1b ack p s send-byte format read-byte format figure 14. smbus protocols
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 24 ______________________________________________________________________________________ ctl/scl is low, except for the start and stop condi- tions. data is transmitted in 8-bit words and is sampled on the rising edge of ctl/scl. nine clock cycles are required to transfer each byte in or out of the max1895 since either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. if the max1895 receives its correct slave address followed by r w = 0, it expects to receive one or two bytes of information (depending on the protocol). if the device detects a start or stop condition prior to clocking in the bytes of data, it considers this an error condition and disregards all of the data. if the transmission is com- pleted correctly the registers are updated immediately after a stop (or restart) condition. if the max1895 receives its correct slave address followed by r w = 1, it expects to clock out the register data selected by the previous command byte. smbus commands the max1895 registers are accessible through several different redundant commands (i.e., the command-byte in the read-byte and write-byte protocols), which can be used to read or write the brightness, shmd, status, or id registers. table 6 summarizes the command-byte s register assignments as well as each register s power-on state. the max1895 also supports the receive-byte protocol for quicker data transfers. this protocol accesses the register configuration pointed to by the last command byte. immediately after power-up, the data-byte returned by the receive-byte protocol is the contents of the brightness register, left justified (i.e. bright4 will be in the most significant bit position of the data byte) with the remaining bits containing a one, status1, and figure 15. smbus write timing smbclk ab cd e fg h i j k smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t hd:dat t su:sto t buf a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low l m f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = slave pulls smbdata line low j = acknowledge clocked into master k = acknowledge clock pulse l = stop condition, data executed by slave m = new start condition figure 16. smbus read timing smbclk a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave ab cd e fg h i j smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t su:dat t su:sto t buf k e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master i = acknowledge clock pulse j = stop condition k = new start condition
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 25 status0. this will give the same result as using the read-word protocol with 0b10xxxxxx (0x80) com- mand. use caution with the shorter protocols in multi- master systems, since a second master could overwrite the command byte without informing the first master. during shutdown the serial interface remains fully functional. brightness register [bright4?right0] (por = 0b10111) the 5-bit brightness register corresponds with the 5-bit brightness code used in the dimming control (see dimming control ). bright4 bright0 = 0b00000 sets minimum brightness and bright4 bright0 = 0b11111 sets maximum brightness. the smbus inter- face does not control whether the device regulates the current by analog dimming, dpwm dimming or both, this is done by mindac (see multimode pin description section) shutdown mode register [shmd2?hmd0] (por = 0b001) the 3-bit shutdown mode register configures the oper- ation of the device when sh /sus pin is toggled as described in table 8. the shutdown mode register can also be used to directly shut off the ccfl regardless of the state of sh /sus (table 9). status register [status1?tatus0] (por = 0b11) the status register returns information on fault condi- tions. if a lamp is not connected to the secondary of the transformer, the max1895 will detect that the lamp current has not exceeded the ifb detection threshold and after 2s will clear the status1 bit (see lamp-out detection section). the status1 bit is latched; i.e. it will remain 0 even if the lamp-out condition goes away. when status1 = 0, the lamp is forced off. status0 reports 1 as long as no overcurrent conditions are detected. if an overcurrent condition is detected in any given digital pwm period, status0 is cleared for the duration of the following digital pwm period. if an over- current condition is not detected in any given digital pwm period, status0 is set for the duration of the fol- lowing digital pwm period. forcing the ccfl lamp off by entering shutdown, writing to the mode register, or by toggling shb/sus sets status1. table 7. command byte description data register bit assignment smbus protocol command byte* por state bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) read and write byte 0x01 0b0xxx xx01 0x17 000 bright4 (msb) bright3 bright2 bright1 bright0 (lsb) read and write byte 0x02 0b0xxx xx10 0xf9 status1 status0 11 1 shmd2 shmd1 shmd0 read byte only 0x03 0b0xxx xx11 0x96 chipid7 1 chipid6 0 chipid5 0 chipid4 1 chipid3 0 chipid2 1 chipid1 1 chipid0 0 read byte only 0x04 0b0xxx xx00 0x00 chiprev7 0 chiprev6 0 chiprev5 0 chiprev4 0 chiprev3 0 chiprev2 0 chiprev1 0 chiprev0 0 read and write byte 0x80 0b10xx xx0x 0xbf bright4 (msb) bright3 bright2 bright1 bright0 (lsb) 1 status1 status0 read byte only 0xfe 0b11xx xxx0 0x4d mfgid7 0 mfgid6 1 mfgid5 0 mfgid4 0 mfgid3 1 mfgid2 1 mfgid1 0 mfgid0 1 read byte only 0xff 0b11xx xxx1 0x96 chipid7 1 chipid6 0 chipid5 0 chipid4 1 chipid3 0 chipid2 1 chipid1 1 chipid0 0 note: the hexadecimal command byte shown is recommended for maximum forward compatibility with future products. x = don t care
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 26 ______________________________________________________________________________________ id registers the id registers return information on the manufacturer, the chip id, and the chip revision number. the max1895 is the first-generation advanced ccfl con- troller and its chiprev is 0x00. reading from mfgid register returns 0x4d, which is the ascii code for m (for maxim), the chipid register returns 0x96. writing to these registers has no effect. chip information transistor count: 7364 table 8. shmd register bit descriptions bit name por state description 2 shmd2 0 shmd2 = 1 forces the lamp off and sets status1. shmd2 = 0 allows the lamp to operate although it may still be shutdown by the sh /sus pin (depending on the state of shmd1 and shmd0). 1 shmd1 0 when sh /sus = 0, this bit has no effect. sh /sus = 1 and shmd1 = 1 forces the lamp off and sets status1. sh /sus = 1 and shmd1 = 0 allows the lamp to operate although it may still be shutdown by the shmd2 bit. 0 shmd0 1 when sh /sus = 1, this bit has no effect. sh /sus = 0 and shmd0 = 1 forces the lamp off and sets status1. sh /sus = 0 and shmd0 = 0 allows the lamp to operate although it may still be shutdown by the shmd2 bit. table 9. sh /sus and shmd register truth table sh /sus shmd2 shmd1 shmd0 operating mode 0 0 x 0 operate 0 0 x 1 shutdown, status1 set 1 0 0 x operate 1 0 1 x shutdown, status1 set x 1 x x shutdown, status1 set x = don t care. table 10. status register bit descriptions (read only/writes have no effect) bit name por state description 1 status1 1 status1 = 0 means that a lamp-out condition has been detected. the status1 bit stays clear even after the lamp-out condition has gone away. the only way to set status1 is to shut off the lamp by programming the mode register or by toggling shb/sus. 0 status0 1 status0 = 0 means that an overcurrent condition was detected during the previous digital pwm period. status0 = 1 means that no overcurrent condition was detected during the previous digital pwm period.
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 27 top view 28 27 26 25 24 23 22 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7 6 5 4 3 2 1 max1995 thin qfn ref ilim mindac gnd mode crf ctl v cc batt ccv cci ifb n.c. v fb gh2 lx2 bst2 bst1 lx1 gh1 gl1 gl2 pgnd v dd n.c. n.c. n.c. sh pin configurations (continued)
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 28 ______________________________________________________________________________________ 32l qfn.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers ______________________________________________________________________________________ 29 package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers 30 ______________________________________________________________________________________ qfn thin 5x5x0.8 .eps d2 (nd-1) x e e d c pin # 1 i.d. (ne-1) x e e/2 e 0.08 c 0.10 c a a1 a3 detail a 0.15 c b 0.15 c a document control no. 21-0140 package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm proprietary information approval title: c rev. 2 1 e2/2 e2 0.10 m c a b pin # 1 i.d. b 0.35x45 l d/2 d2/2 l c l c e e l c c l k k l l package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max1895/max1995 high-efficiency, wide brightness range, ccfl backlight controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 31 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. 2 2 21-0140 rev. document control no. approval proprietary information title: common dimensions exposed pad variations 1. dimensioning & tolerancing conform to asme y14.5m-1994. 2. all dimensions are in millimeters. angles are in degrees. 3. n is the total number of terminals. 4. the terminal #1 identifier and terminal numbering convention shall conform to jesd 95-1 spp-012. details of terminal #1 identifier are optional, but must be located within the zone indicated. the terminal #1 identifier may be either a mold or marked feature. 5. dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from terminal tip. 6. nd and ne refer to the number of terminals on each d and e side respectively. 7. depopulation is possible in a symmetrical fashion. 8. coplanarity applies to the exposed heat sink slug as well as the terminals. 9. drawing conforms to jedec mo220. notes: 10. warpage shall not exceed 0.10 mm. c package outline 16, 20, 28, 32l, qfn thin, 5x5x0.8 mm package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)

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